FPGA Simulation of Bit-Count Comparator Based Modified Design of Viterbi Decoder for Burst Error Detection

In the wireless data communication the signals present in the transmission environment interfere with the communicating signals causing an undesired signal reception. This may further cause processing of wrong data. So the transmission error sensitive communication systems are always in need of an efficient encoder and decoder hardware interface that are capable of error detection and correction. Convolution encoder and decoder provide an easy to implement hardware in the same direction. The error handling efficiency of different convolution decoders vary with respect to their hardware designs and implemented algorithm for error detection and correction. Viterbi decoder provides one of the efficient techniques of error detection and correction to the communication systems. It is a Trellis code modulation decoder. There are various hardware implementations of viterbi decoder. A rate 1/3 decoder is a technique that encodes a single bit data in a 3-bit encoded data. This encoded data is decoded to effectively detect and correct single bit error with perfect efficiency. But the effects of burst error are not effectively judged using the technique because of the un-predictability of random effects of the burst error on the transmission data. In the proposed work a modified design of Viterbi decoder is simulated on a field programmable gate array device with the concept of burst error identification. In the proposed design, logical bit count comparator hardware is used to count the number of logic-‘1’ and logic-‘0’ and to transfer the information using a single-bit with the transmission data towards the receiver end. At the receiver, the same information is derived from the decoded data to authenticate the absence of the burst error with respect to the encoded data. A comparison of the conventional viterbi decoder simulation result and the proposed design is also presented in this work. The present work shows the simulation result with burst error identification using the proposed concept.